Lead Logic Design Engineer
Astera Labs, Bengaluru, Karnataka, India
Salary not disclosed
Lead levelFirmware
You will lead RTL and microarchitecture development for UALink-based IP and subsystems, translating protocol requirements into high-performance, low-latency interconnect designs. The role requires 6–10 years of experience and deep expertise in control logic, data-path optimization, and protocol implementation.
Posted September 10, 2026 (3w ago)