Lead Logic Design Engineer
Astera Labs, Bengaluru, Karnataka, India
Salary not disclosed
Lead levelFirmware
You will lead RTL and microarchitecture development for complex PCIe-based IP and subsystems, translating specifications into high-performance connectivity designs and optimizing for area, power, and latency. The role requires 6–10 years of experience and deep expertise in protocol implementation, control logic, and silicon bring-up.
Posted September 17, 2026 (2w ago)