STA Physical Design Engineer, Senior Principal
Astera Labs, San Jose, California, United States
$207,000 – $230,000 / year
above the median for senior electronics roles
Senior levelElectronics
You will drive planning and execution of static timing analysis and sign-off for complex connectivity ASICs from RTL to GDS, collaborating closely with RTL and verification teams. You need deep STA expertise, RTL-to-GDS ownership experience, and the ability to ensure robust full-chip signoff.
Posted February 24, 2026 (7mo ago)