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Senior DFT Engineer, Architecture

TETenstorrent, Tokyo, Japan

You will lead the design-for-test strategy and implementation for high-speed RISC-V CPU designs integrated into system-in-package configurations. Your responsibilities include inserting test features such as scan chains, memory BIST, and JTAG while collaborating with RTL, physical design, and verification teams.

Posted November 5, 2024 (23mo ago)