Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)
Tenstorrent, Santa Clara, California, United States
$100,000 – $500,000 / year
above the median for senior electronics roles
Senior levelElectronics
You will drive physical implementation of die-to-die interfaces for multi-die AI SOCs, closing high-speed connections across chiplets from RTL to GDSII. You need 5+ years of advanced-node ASIC physical design experience with multiple successful tapeouts.
Posted February 27, 2026 (7mo ago)