Senior Principal ASIC Design Engineer
Astera Labs, Germany (Onsite)
Salary not disclosed
Principal levelElectronics
The Senior Principal ASIC Design Engineer will lead full-stack chip architecture and implementation for next-generation AI connectivity products, setting technical direction across design methodologies and mentoring senior engineers. The role spans high-speed Ethernet, UALink, and PCIe Gen 6/7 with accountability for robust, manufacturerable silicon.
Posted August 2, 2026 (2mo ago)