(India) System IP Design Engineer
Tenstorrent, Bengaluru, Karnataka, India
Salary not disclosed
Electronics
Design and optimize microarchitecture and RTL for power management subsystems and interconnect controllers in next-generation SoCs. Requires 5–10 years in ASIC/SOC design with hands-on SystemVerilog and cross-functional collaboration.
Posted June 22, 2026 (3mo ago)