Principal Product Technical Leader — AEC/SCM
Astera Labs, San Jose, California, United States
Salary not disclosed
Lead levelElectronics
Own RTL design and implementation of complex digital blocks for AI infrastructure connectivity silicon, leading design execution across PCIe, CXL, and emerging interconnect standards. Requires strong SystemVerilog skills and experience taking features from specification to silicon.
Posted August 4, 2026 (2mo ago)