Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet
Astera Labs, Taipei, Taiwan
Salary not disclosed
Principal levelTesting
You will lead verification strategy and methodology improvements for next-generation connectivity IPs and SoCs, mentoring engineering teams and collaborating across architecture, RTL, and silicon teams. This highly visible technical leadership role focuses on defining comprehensive verification approaches to ensure first-pass silicon success.
Posted September 14, 2026 (3w ago)