Formal Verification - DV
Etched, San Jose
Salary not disclosed
Testing
You will define and drive formal verification strategy across custom IP blocks, interface subsystems, and SoC integration logic for AI ASICs using formal methods and assertions. You need expertise in formal verification methodologies, SystemVerilog, and ability to work across architecture, RTL, DV, and software teams.
Posted June 10, 2026 (4mo ago)