Principal Physical Design Engineer, STA
Astera Labs, San Jose, California, United States
$209,000 – $250,000 / year
above the median for principal electronics roles
Principal levelElectronics
You will drive timing closure from RTL through sign-off for complex AI connectivity ASICs, developing and validating timing constraints and collaborating with RTL, physical design, and verification teams to ensure robust convergence. You need deep expertise in STA methodologies, timing analysis tools, and full-chip timing convergence on advanced nodes.
Posted May 20, 2026 (4mo ago)