Principal Physical Design Engineer, Methodology
Astera Labs, San Jose, California, United States
$185,000 – $240,000 / year
about the median for principal electronics roles
Principal levelElectronics
You will define and maintain reusable physical design flows and automation infrastructure supporting the entire physical design team, integrating tools from multiple vendors and improving PPA predictability across all chip programs. You need expertise in building scalable design methodologies, RTL-to-GDSII flows, and tool integration across Cadence and Synopsys platforms.
Posted July 22, 2026 (2mo ago)