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Principal Logic Design Engineer - UALink IP/Subsystem

Astera Labs, Bengaluru, Karnataka, India

Salary not disclosed

Lead levelElectronics

You will lead RTL and microarchitecture development for UALink IP subsystems, translating protocol and system requirements into scalable hardware architectures. You need 10-15 years of experience in high-performance interconnect and SoC/IP design with expertise in data path design and reliability mechanisms.

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Posted September 17, 2026 (2w ago)

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