Principal IP Signoff & Methodology Engineer
Astera Labs, San Jose, California, United States
$175,000 – $230,000 / year
below the median for lead electronics roles
Lead levelElectronics
You will own the readiness and quality signoff of internal and external IP blocks before SoC integration, ensuring complete and validated deliverables. You need expertise in RTL, physical design, timing closure, and integration-ready IP handoff across multiple design views.
Posted April 29, 2026 (5mo ago)