Principal Design Verification Engineer
Astera Labs, Bengaluru, Karnataka, India
Salary not disclosed
Principal levelTesting
You will lead functional verification of advanced ASIC designs with expertise in PCIe and CXL protocols, from test planning through coverage closure. You need strong SystemVerilog skills and protocol expertise to develop comprehensive verification methodologies for complex SoC designs.
Posted August 27, 2026 (5w ago)