DFT (Design For Test) Engineer
Etched, San Jose
$150,000 – $275,000 / year
above the median for testing roles
Testing
You will develop and implement Design for Test architectures for ASIC and SoC designs, integrating industry-standard DFT methodologies to enhance test coverage and debug capability. You need expertise in scan insertion, BIST, MBIST, and silicon debug analysis to drive improvements in yield and reliability.
Posted February 28, 2026 (7mo ago)