RTL Design Engineer
Etched, San Jose
$150,000 – $275,000 / year
above the median for mid firmware roles
Mid levelFirmware
You will develop and implement design verification strategies for Etched's ASIC designs, working with state-of-the-art ML architectures and ensuring correct and efficient chip operation. You need at least 5 years of RTL development experience, proficiency in synthesis tools, and familiarity with verification methodologies.
Posted June 11, 2025 (16mo ago)