Design Verification Engineer
SambaNova Systems, San Jose, California, United States
$120,000 – $200,000 / year
below the median for testing roles
Testing
Build SystemVerilog and UVM verification environments for AI accelerator chips, owning verification plans from development through closure. Debug and root-cause issues across chip-level control, initialization, and multi-subsystem coordination.
Posted August 18, 2026 (7w ago)