Tech Lead, Digital Design Engineer
Astera Labs, San Jose, California, United States
Salary not disclosed
Electronics
Lead front-end digital design for high-performance connectivity ASICs, managing RTL implementation and verification methodologies. Requires deep expertise in Cadence flows, DFT, UVM verification, and design of PCIe or Ethernet switching products at small-geometry nodes.
Posted September 28, 2026 (4d ago)