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Design Verification Tech Lead- SerDes/PHY IP

Astera Labs, San Jose, California, United States

Salary not disclosed

Lead levelTesting

The Design Verification Tech Lead oversees verification strategies and execution for SerDes/PHY IP blocks used in connectivity solutions. They need extensive experience in digital verification, SystemVerilog, and semiconductor design with leadership of verification teams.

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Posted September 21, 2026 (11d ago)

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